ds_read2st64_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_read2st64_b32

Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…

Also written as ds_load_2addr_stride64_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00111000
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 56 in OP rebuilds 0x00000000D8700000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 56
Identifier 0x00000000D8700000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK2_B32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

Semantics

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 256U].b32; addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 256U].b32

Example

ds_read2st64_b32 v[5:6], v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources