ds_read_b96_tr_b6 GPU Native ISA AMD Vector

LDS / Data Share

ds_read_b96_tr_b6

Read 96 bits of data per lane from data share.

Also written as ds_read_b128_tr_b6. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
11100001
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 225 in OP rebuilds 0x00000000D9C20000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format DS
Width 64 bits
Opcode 225
Identifier 0x00000000D9C20000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B96)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Read 96 bits of data per lane from data share. Interpret the data as a matrix with 6 bit elements and transpose the matrix. Store the result into vector registers.

Sources