ds_read_b96_tr_b6 GPU Native ISA AMD Vector

DS READ B96 TR B6 LDS / Data Share

ds_read_b96_tr_b6

Read 96 bits of data per lane from data share.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Read 96 bits of data per lane from data share. Interpret the data as a matrix with 6 bit elements and transpose the matrix. Store the result into vector registers.

Sources