ds_read_i16 GPU Native ISA AMD Vector
DS READ I16 LDS / Data Share
ds_read_i16
Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Semantics
RETURN_DATA.i32 = 32'I(signext(MEM[ADDR].i16))
Example
ds_read_i16 v5, v1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 433. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project