ds_ordered_count GPU Native ISA AMD Vector

LDS / Data Share

ds_ordered_count

GDS-only.

Encoding

Binary Layout (AMD CDNA 1)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
unassigned
25
10111111
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 1). Opcode 191 in OP rebuilds 0x00000000D97E0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (opcode 63, field layout), AMD RDNA 3 (opcode 63, field layout), AMD RDNA 2 (opcode 63, field layout), AMD RDNA 1 (opcode 63, field layout).

Format DS
Width 64 bits
Opcode 191
Identifier 0x00000000D97E0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 1).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

GDS-only. Add (count_bits(exec_mask)) to one of 4 dedicated ordered-count counters (aka 'packers'). Additional bits of instr.offset field are overloaded to hold packer-id, 'last'.

Example

ds_ordered_count v5, v1 gds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources