ds_mskor_rtn_b32 GPU Native ISA AMD Vector
DS MSKOR RTN B32 LDS / Data Share
ds_mskor_rtn_b32
Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Semantics
addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].b32;
MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32);
RETURN_DATA.b32 = tmp
Example
ds_mskor_rtn_b32 v5, v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 428. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project