ds_min_num_rtn_f32 GPU Native ISA AMD Vector

DS MIN NUM RTN F32 LDS / Data Share

ds_min_num_rtn_f32

Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value. Store the original value from data share into a vector register.

Sources