ds_max_num_f32 GPU Native ISA AMD Vector

LDS / Data Share

ds_max_num_f32

Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share.

Also written as ds_max_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
00010011
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 19 in OP rebuilds 0x00000000D84C0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 19
Identifier 0x00000000D84C0000

Operands

  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.

Example

ds_max_num_f32 v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_ds.s). Not from an AMD document, and not authored here.

Sources