ds_pk_add_rtn_bf16 GPU Native ISA AMD Vector

DS PK ADD RTN BF16 LDS / Data Share

ds_pk_add_rtn_bf16

Add a packed 2-component BF16 float value in the data register to a location in a data share.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Floating-point addition handles NAN/INF/denorm.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Add a packed 2-component BF16 float value in the data register to a location in a data share. Store the original value from data share into a vector register.

Semantics

tmp = MEM[ADDR]; src = DATA; dst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16; dst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16; MEM[ADDR] = dst.b32; RETURN_DATA = tmp

Sources