ds_read_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_read_b32 VDST, ADDR, offset

Read one 32-bit value per lane from the Local Data Share (LDS).

Also written as ds_load_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00110110
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 54 in OP rebuilds 0x00000000D86C0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 54
Identifier 0x00000000D86C0000
Execution Unit LDS Unit
Register Classes VGPR
Memory Segment LDS/shared

Operands

  • VDST
    Destination VGPR
  • ADDR
    Per-lane LDS byte address (VGPR)
  • offset
    Immediate byte offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Shared/Local-Memory Load ↗
equivalent with restrictions
ld (PTX)

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from a data share into a vector register.

Semantics

VDST[lane] = LDS[ADDR[lane] + offset] for each active lane.

Example

ds_read_b32  v1, v0   // v1 = LDS[v0]

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources