ds_read_b32 GPU Native ISA AMD Vector

DS READ B32 LDS / Data Share

ds_read_b32 VDST, ADDR, offset

Read one 32-bit value per lane from the Local Data Share (LDS).

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Width 32 bits
Execution Unit LDS Unit
Register Classes VGPR
Memory Segment LDS/shared

Operands

  • VDST
    Destination VGPR
  • ADDR
    Per-lane LDS byte address (VGPR)
  • offset
    Immediate byte offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Shared/Local-Memory Load ↗
equivalent with restrictions
ld (PTX)

Reference

AMDGPU / GFX ISA

Semantics

VDST[lane] = LDS[ADDR[lane] + offset] for each active lane.

Sources