ds_pk_add_bf16 GPU Native ISA AMD Vector

LDS / Data Share

ds_pk_add_bf16

Add a packed 2-component BF16 float value in the data register to a location in a data share.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
10011011
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 155 in OP rebuilds 0x00000000DA6C0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_DS, opcode 24, field layout), AMD CDNA 3 (encoding ENC_DS, opcode 24, field layout). The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 155
Identifier 0x00000000DA6C0000

Operands

  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit brain floating point value. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_BF16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Floating-point addition handles NAN/INF/denorm.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

tmp = MEM[ADDR]; src = DATA; dst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16; dst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16; MEM[ADDR] = dst.b32; RETURN_DATA = tmp

Example

ds_pk_add_bf16 v0, v0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_ds.s). Not from an AMD document, and not authored here.

Sources