ds_read_i8 GPU Native ISA AMD Vector

LDS / Data Share

ds_read_i8

Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register.

Also written as ds_load_i8. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00111001
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 57 in OP rebuilds 0x00000000D8720000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 57
Identifier 0x00000000D8720000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_I32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

RETURN_DATA.i32 = 32'I(signext(MEM[ADDR].i8))

Example

ds_read_i8 v5, v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources