LDS / Data Share Instructions
233 AMDGPU instructions in this category - showing 100 per page, page 2 of 3 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ds_max_rtn_u64 | ds_max_rtn_u64 | DS | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_src2_f32 | ds_max_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_f64 | ds_max_src2_f64 | DS | AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_i32 | ds_max_src2_i32 | DS | AMDGPU DS vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_i64 | ds_max_src2_i64 | DS | AMDGPU DS vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_u32 | ds_max_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_u64 | ds_max_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_u32 | ds_max_u32 | DS | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_u64 | ds_max_u64 | DS | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_f32 | ds_min_f32 | DS | Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_f64 | ds_min_f64 | DS | Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_i32 | ds_min_i32 | DS | Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_i64 | ds_min_i64 | DS | Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_num_f32 | ds_min_num_f32 | DS | Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_num_f64 | ds_min_num_f64 | DS | Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_num_rtn_f32 | ds_min_num_rtn_f32 | DS | Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_num_rtn_f64 | ds_min_num_rtn_f64 | DS | Select the IEEE minimumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_f32 | ds_min_rtn_f32 | DS | Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_f64 | ds_min_rtn_f64 | DS | Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_i32 | ds_min_rtn_i32 | DS | Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_i64 | ds_min_rtn_i64 | DS | Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_u32 | ds_min_rtn_u32 | DS | Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_rtn_u64 | ds_min_rtn_u64 | DS | Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_src2_f32 | ds_min_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_src2_f64 | ds_min_src2_f64 | DS | AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_src2_i32 | ds_min_src2_i32 | DS | AMDGPU DS vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_src2_i64 | ds_min_src2_i64 | DS | AMDGPU DS vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_src2_u32 | ds_min_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_src2_u64 | ds_min_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_min_u32 | ds_min_u32 | DS | Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_min_u64 | ds_min_u64 | DS | Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_mskor_b32 | ds_mskor_b32 | DS | Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers. |
| ds_mskor_b64 | ds_mskor_b64 | DS | Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers. |
| ds_mskor_rtn_b32 | ds_mskor_rtn_b32 | DS | Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers. |
| ds_mskor_rtn_b64 | ds_mskor_rtn_b64 | DS | Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers. |
| ds_nop | ds_nop | DS | Do nothing. |
| ds_or_b32 | ds_or_b32 | DS | Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. |
| ds_or_b64 | ds_or_b64 | DS | Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_or_rtn_b32 | ds_or_rtn_b32 | DS | Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. |
| ds_or_rtn_b64 | ds_or_rtn_b64 | DS | Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_or_src2_b32 | ds_or_src2_b32 | DS | AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_or_src2_b64 | ds_or_src2_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_ordered_count | ds_ordered_count | DS | GDS-only. |
| ds_pk_add_bf16 | ds_pk_add_bf16 | DS | Add a packed 2-component BF16 float value in the data register to a location in a data share. |
| ds_pk_add_f16 | ds_pk_add_f16 | DS | Add a packed 2-component half-precision float value in the data register to a location in a data share. |
| ds_pk_add_rtn_bf16 | ds_pk_add_rtn_bf16 | DS | Add a packed 2-component BF16 float value in the data register to a location in a data share. |
| ds_pk_add_rtn_f16 | ds_pk_add_rtn_f16 | DS | Add a packed 2-component half-precision float value in the data register to a location in a data share. |
| ds_read2_b32 | ds_read2_b32 | DS | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… |
| ds_read2_b64 | ds_read2_b64 | DS | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… |
| ds_read2st64_b32 | ds_read2st64_b32 | DS | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… |
| ds_read2st64_b64 | ds_read2st64_b64 | DS | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… |
| ds_read_addtid_b32 | ds_read_addtid_b32 | DS | Load 32 bits of data from a data share into a vector register. |
| ds_read_b128 | ds_read_b128 | DS | Load 128 bits of data from a data share into a vector register. |
| ds_read_b32 | ds_read_b32 VDST, ADDR, offset | DS | Read one 32-bit value per lane from the Local Data Share (LDS). |
| ds_read_b64 | ds_read_b64 | DS | Load 64 bits of data from a data share into a vector register. |
| ds_read_b64_tr_b16 | ds_read_b64_tr_b16 | DS | Read 64 bits of data per lane from data share. |
| ds_read_b64_tr_b4 | ds_read_b64_tr_b4 | DS | Read 64 bits of data per lane from data share. |
| ds_read_b64_tr_b8 | ds_read_b64_tr_b8 | DS | Read 64 bits of data per lane from data share. |
| ds_read_b96 | ds_read_b96 | DS | Load 96 bits of data from a data share into a vector register. |
| ds_read_b96_tr_b6 | ds_read_b96_tr_b6 | DS | Read 96 bits of data per lane from data share. |
| ds_read_i16 | ds_read_i16 | DS | Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. |
| ds_read_i8 | ds_read_i8 | DS | Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. |
| ds_read_i8_d16 | ds_read_i8_d16 | DS | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register. |
| ds_read_i8_d16_hi | ds_read_i8_d16_hi | DS | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register. |
| ds_read_u16 | ds_read_u16 | DS | Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. |
| ds_read_u16_d16 | ds_read_u16_d16 | DS | Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register. |
| ds_read_u16_d16_hi | ds_read_u16_d16_hi | DS | Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register. |
| ds_read_u8 | ds_read_u8 | DS | Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. |
| ds_read_u8_d16 | ds_read_u8_d16 | DS | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register. |
| ds_read_u8_d16_hi | ds_read_u8_d16_hi | DS | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register. |
| ds_rsub_rtn_u32 | ds_rsub_rtn_u32 | DS | Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. |
| ds_rsub_rtn_u64 | ds_rsub_rtn_u64 | DS | Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. |
| ds_rsub_src2_u32 | ds_rsub_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_rsub_src2_u64 | ds_rsub_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_rsub_u32 | ds_rsub_u32 | DS | Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. |
| ds_rsub_u64 | ds_rsub_u64 | DS | Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. |
| ds_store_2addr_b32 | ds_store_2addr_b32 | DS | Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. |
| ds_store_2addr_b64 | ds_store_2addr_b64 | DS | Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. |
| ds_store_2addr_stride64_b32 | ds_store_2addr_stride64_b32 | DS | Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. |
| ds_store_2addr_stride64_b64 | ds_store_2addr_stride64_b64 | DS | Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. |
| ds_store_addtid_b32 | ds_store_addtid_b32 | DS | Store 32 bits of data from a vector input register into a data share. |
| ds_store_b128 | ds_store_b128 | DS | Store 128 bits of data from a vector input register into a data share. |
| ds_store_b16 | ds_store_b16 | DS | Store 16 bits of data from a vector register into a data share. |
| ds_store_b16_d16_hi | ds_store_b16_d16_hi | DS | Store 16 bits of data from the high bits of a vector register into a data share. |
| ds_store_b32 | ds_store_b32 | DS | Store 32 bits of data from a vector input register into a data share. |
| ds_store_b64 | ds_store_b64 | DS | Store 64 bits of data from a vector input register into a data share. |
| ds_store_b8 | ds_store_b8 | DS | Store 8 bits of data from a vector register into a data share. |
| ds_store_b8_d16_hi | ds_store_b8_d16_hi | DS | Store 8 bits of data from the high bits of a vector register into a data share. |
| ds_store_b96 | ds_store_b96 | DS | Store 96 bits of data from a vector input register into a data share. |
| ds_storexchg_2addr_rtn_b32 | ds_storexchg_2addr_rtn_b32 | DS | Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. |
| ds_storexchg_2addr_rtn_b64 | ds_storexchg_2addr_rtn_b64 | DS | Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. |
| ds_storexchg_2addr_stride64_rtn_b32 | ds_storexchg_2addr_stride64_rtn_b32 | DS | Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. |
| ds_storexchg_2addr_stride64_rtn_b64 | ds_storexchg_2addr_stride64_rtn_b64 | DS | Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. |
| ds_storexchg_rtn_b32 | ds_storexchg_rtn_b32 | DS | Swap an unsigned 32-bit integer value in the data register with a location in a data share. |
| ds_storexchg_rtn_b64 | ds_storexchg_rtn_b64 | DS | Swap an unsigned 64-bit integer value in the data register with a location in a data share. |
| ds_sub_clamp_rtn_u32 | ds_sub_clamp_rtn_u32 | DS | Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero. |
| ds_sub_clamp_u32 | ds_sub_clamp_u32 | DS | Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero. |
| ds_sub_gs_reg_rtn | ds_sub_gs_reg_rtn | DS | Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly. |
| ds_sub_rtn_u32 | ds_sub_rtn_u32 | DS | Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share. |
| ds_sub_rtn_u64 | ds_sub_rtn_u64 | DS | Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share. |