ds_sub_gs_reg_rtn GPU Native ISA AMD Vector

LDS / Data Share

ds_sub_gs_reg_rtn

Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly.

Encoding

Binary Layout (AMD RDNA 3.5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
01111011
25:18
GDS
17
unassigned
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 123 in OP rebuilds 0x00000000D9EC0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 3.

Format DS
Width 64 bits
Opcode 123
Identifier 0x00000000D9EC0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B64)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Perform an atomic subtraction from data in specific registers embedded in GDS rather than operating on GDS memory directly. This instruction returns the pre-op value. This instruction is only used by the GS stage and is used to facilitate streamout.

Example

ds_sub_gs_reg_rtn v[5:6], v1 gds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources