ds_write2_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_write2_b32

Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.

Also written as ds_store_2addr_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00001110
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 14 in OP rebuilds 0x00000000D81C0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 14
Identifier 0x00000000D81C0000

Operands

  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)
  • DATA1
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); MEM[addr + OFFSET0.u32 * 4U].b32 = DATA[31 : 0]; addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); MEM[addr + OFFSET1.u32 * 4U].b32 = DATA2[31 : 0]

Example

ds_write2_b32 v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources