ds_wrxchg2_rtn_b64 GPU Native ISA AMD Vector

LDS / Data Share

ds_wrxchg2_rtn_b64

Swap two unsigned 64-bit integer values in the data registers with two locations in a data share.

Also written as ds_storexchg_2addr_rtn_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
01101110
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 110 in OP rebuilds 0x00000000D8DC0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 110
Identifier 0x00000000D8DC0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK2_B64)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B64)
  • DATA1
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

addr1 = ADDR_BASE.u32 + OFFSET0.u32 * 8U; addr2 = ADDR_BASE.u32 + OFFSET1.u32 * 8U; tmp1 = MEM[addr1].b64; tmp2 = MEM[addr2].b64; MEM[addr1].b64 = DATA.b64; MEM[addr2].b64 = DATA2.b64; // Note DATA2 can be any other register RETURN_DATA[63 : 0] = tmp1; RETURN_DATA[127 : 64] = tmp2

Example

ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources