ds_wrxchg_rtn_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_wrxchg_rtn_b32

Swap an unsigned 32-bit integer value in the data register with a location in a data share.

Also written as ds_storexchg_rtn_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00101101
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 45 in OP rebuilds 0x00000000D85A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 45
Identifier 0x00000000D85A0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Atomic Exchange ↗
equivalent with restrictions
atom (PTX)

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); tmp = MEM[addr].b32; MEM[addr].b32 = DATA.b32; RETURN_DATA.b32 = tmp

Example

ds_wrxchg_rtn_b32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources