ds_write_b32 GPU Native ISA AMD Vector
DS WRITE B32 LDS / Data Share
ds_write_b32 ADDR, DATA, offset
Write one 32-bit value per lane to the Local Data Share (LDS).
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
-
ADDR
Per-lane LDS byte address (VGPR) -
DATA
Per-lane value to write (VGPR) -
offset
Immediate byte offset
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx942 | ✅ Supported |
| gfx1100 | ✅ Supported |
Related PTX Concepts
Reference
AMDGPU / GFX ISA
Semantics
LDS[ADDR[lane] + offset] = DATA[lane] for each active lane.
Sources
- ROCm Documentation ↗ — Advanced Micro Devices, Inc.
- User Guide for AMDGPU Backend ↗ — LLVM Project