ds_write_b32 GPU Native ISA AMD Vector

DS WRITE B32 LDS / Data Share

ds_write_b32 ADDR, DATA, offset

Write one 32-bit value per lane to the Local Data Share (LDS).

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Width 32 bits
Execution Unit LDS Unit
Register Classes VGPR
Memory Segment LDS/shared

Operands

  • ADDR
    Per-lane LDS byte address (VGPR)
  • DATA
    Per-lane value to write (VGPR)
  • offset
    Immediate byte offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Shared/Local-Memory Store ↗
equivalent with restrictions
st (PTX)

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Store 32 bits of data from a vector input register into a data share.

Semantics

LDS[ADDR[lane] + offset] = DATA[lane] for each active lane.

Example

ds_write_b32  v0, v1   // LDS[v0] = v1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources