ds_wrap_rtn_b32 GPU Native ISA AMD Vector
DS WRAP RTN B32 LDS / Data Share
ds_wrap_rtn_b32
Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
This instruction is designed to for use in ring buffer management.
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative; otherwise add a value from a second vector register to the memory location. This calculation provides flexible wraparound semantics for subtraction.
Semantics
tmp = MEM[ADDR].u32;
MEM[ADDR].u32 = tmp >= DATA.u32 ? tmp - DATA.u32 : tmp + DATA2.u32;
RETURN_DATA = tmp
Example
ds_wrap_rtn_b32 v5, v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 431. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project