ds_wrap_rtn_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_wrap_rtn_b32

Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative…

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00110100
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 52 in OP rebuilds 0x00000000D8680000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 52
Identifier 0x00000000D8680000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)
  • DATA1
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This instruction is designed to for use in ring buffer management.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative; otherwise add a value from a second vector register to the memory location. This calculation provides flexible wraparound semantics for subtraction.

Semantics

tmp = MEM[ADDR].u32; MEM[ADDR].u32 = tmp >= DATA.u32 ? tmp - DATA.u32 : tmp + DATA2.u32; RETURN_DATA = tmp

Example

ds_wrap_rtn_b32 v5, v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources