ds_sub_clamp_rtn_u32 GPU Native ISA AMD Vector

DS SUB CLAMP RTN U32 LDS / Data Share

ds_sub_clamp_rtn_u32

Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Subtract an unsigned 32-bit integer location in a data share from a value in the data register and clamp the result to zero. Store the original value from data share into a vector register.

Sources