ds_storexchg_2addr_stride64_rtn_b32 GPU Native ISA AMD Vector

DS STOREXCHG 2ADDR STRIDE64 RTN B32 LDS / Data Share

ds_storexchg_2addr_stride64_rtn_b32

Swap two unsigned 32-bit integer values in the data registers with two locations in a data share.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

Example

ds_storexchg_2addr_stride64_rtn_b32 v[5:6], v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources