ds_write2st64_b32 GPU Native ISA AMD Vector
DS WRITE2ST64 B32 LDS / Data Share
ds_write2st64_b32
Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.
Semantics
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET0.u32 * 256U].b32 = DATA[31 : 0];
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
MEM[addr + OFFSET1.u32 * 256U].b32 = DATA2[31 : 0]
Example
ds_write2st64_b32 v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 422. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project