ds_write_b16_d16_hi GPU Native ISA AMD Vector

LDS / Data Share

ds_write_b16_d16_hi

Store 16 bits of data from the high bits of a vector register into a data share.

Also written as ds_store_b16_d16_hi. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
01010101
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 85 in OP rebuilds 0x00000000D8AA0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (opcode 161, field layout), AMD RDNA 1 (opcode 161, field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 85
Identifier 0x00000000D8AA0000

Operands

  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_PK2_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

MEM[ADDR].b16 = DATA[31 : 16]

Example

ds_write_b16_d16_hi v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources