atom GPU Virtual ISA NVIDIA

Atomic Read-Modify-Write Parallel Synchronization and Communication Instructions

atom.space.op.type d, [a], b;

Atomically read-modify-write a memory location and return the prior value.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.1
Minimum Target sm_11

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
atom.space.op.type d, [a], b; b32, b64, s32, u32, u64, f32, f64 global, shared add, min, max, and, or, xor, exch, cas, inc, dec sm_11 Atomic operation; op selects the read-modify-write function.

Operands

  • d
    Destination register (receives the pre-operation value)
  • a
    Memory address
  • b
    Operand value

At a Glance

Data Types b32, b64, f32, f64, s32, u32, u64
State Spaces global, shared
Modifiers add, and, cas, dec, exch, inc, max, min, or, xor

Related AMDGPU Concepts

Atomic Add ↗
equivalent with restrictions
ds_add_u32 (AMDGPU)
Atomic Compare-and-Swap ↗
equivalent with restrictions
ds_cmpstore_b32 (AMDGPU)
Atomic Exchange ↗
equivalent with restrictions
Atomic Minimum and Maximum ↗
equivalent with restrictions
ds_min_rtn_i32 (AMDGPU)
Atomic Bitwise Operations ↗
equivalent with restrictions
global_atomic_or (AMDGPU)

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

Atomically loads the original value at location a into destination register d, performs a reduction operation with operand b and the value in location a, and stores the result of the specified operation at location a, overwriting the original value. For the.cas (compare-and-swap) operation, operand b is the compare value and operand c is the swap value. The operation compares the value at location a with operand b; if they are equal, it stores operand c at location a, otherwise it leaves the value at location a unchanged. Operand a specifies a location in the specified state space. If no state space is given, perform the memory accesses using Generic Addressing. (see the official PTX ISA docs for the full description)

Semantics

d = *a; *a = op(*a, b); indivisible with respect to other threads targeting the same address.

Examples

atom.global.add.s32  d,[a],1;
atom.shared::cta.max.u32  d,[x+4],0;
@p  atom.global.cas.b32  d,[p],my_val,my_new_val;
atom.global.sys.add.u32 d, [a], 1;
atom.global.acquire.sys.inc.u32 ans, [gbl], %r0;
atom.add.noftz.f16x2 d, [a], b;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources