atom GPU Virtual ISA NVIDIA

Atomic Read-Modify-Write Atomic Memory

atom.space.op.type d, [a], b;

Atomically read-modify-write a memory location and return the prior value.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_11

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
atom.space.op.type d, [a], b; b32, b64, s32, u32, u64, f32, f64 global, shared add, min, max, and, or, xor, exch, cas, inc, dec sm_11 Atomic operation; op selects the read-modify-write function.

Operands

  • d
    Destination register (receives the pre-operation value)
  • a
    Memory address
  • b
    Operand value

At a Glance

Data Types b32, b64, f32, f64, s32, u32, u64
State Spaces global, shared
Modifiers add, and, cas, dec, exch, inc, max, min, or, xor

Related AMDGPU Concepts

Atomic Add ↗
equivalent with restrictions
ds_add_u32 (AMDGPU)

Reference

NVIDIA PTX ISA

Semantics

d = *a; *a = op(*a, b); indivisible with respect to other threads targeting the same address.

Sources