Atomic Minimum and Maximum Atomics
Atomically replace a memory value with the smaller or larger of it and an operand.
Vendor-Neutral Definition
*addr = min(*addr, val) or max(*addr, val), indivisibly, with signed and unsigned forms that differ in how the comparison treats the high bit.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both provide atomic min and max with separate signed and unsigned forms; the split between them is encoded in the opcode on AMDGPU and in a type suffix on PTX.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | atom, red | global_atomic_smin, global_atomic_umax, ds_min_rtn_i32 |
| ISA Layer | Virtual | Native |
| Data Types | b32, b64, f32, f64, s32, u32, u64 | i32 |
| Version / Target Introduced | PTX ISA 1.1, PTX ISA 1.2 | gfx1100 |
Important Differences
- Signedness is part of the AMDGPU mnemonic (smin against umin), where PTX carries it in the type suffix of atom.min.s32 against atom.min.u32.
- Floating-point atomic min and max are available on both but their support varies by target: check the specific GFX target and the PTX target architecture rather than assuming.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ - LLVM Project
Verification method: documentation