mbarrier.check_layout GPU Virtual ISA NVIDIA

mbarrier.check_layout Parallel Synchronization and Communication Instructions

mbarrier.check_layout.layout{.ss}.b64 p, [addr];

The layout of the opaque mbarrier object can be queried using mbarrier.check_layout.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 9.3
Minimum Target sm_90

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mbarrier.check_layout.layout{.ss}.b64 p, [addr]; sm_90 The layout of the opaque mbarrier object can be queried using mbarrier.check_layout. The address operand addr specifies the memory location of the mbarrier object whose layout is being inspected. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

The layout of the opaque mbarrier object can be queried using mbarrier.check_layout. The address operand addr specifies the memory location of the mbarrier object whose layout is being inspected. The instruction sets the predicate operand p to True if the layout of the mbarrier object exactly matches the.layout qualifier. Refer Layouts of the mbarrier object for more details. If no state space is specified then Generic Addressing is used. If the address specified by addr does not fall within the address window of.shared::cta state space then the behavior is undefined.

Examples

.reg    .pred p;
.shared .b64  shMem;

mbarrier.check_layout.layout::v1.shared::cta.b64 p, [shMem];
@!p bra exit
// ... mbarrier operations on shMem
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources