mbarrier.inval GPU Virtual ISA NVIDIA

mbarrier.inval Parallel Synchronization and Communication Instructions

mbarrier.inval{.shared{::cta}}.b64 [addr];

mbarrier.inval invalidates the mbarrier object at the location specified by the address operand addr.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.0
Minimum Target sm_80

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mbarrier.inval{.shared{::cta}}.b64 [addr]; sm_80 mbarrier.inval invalidates the mbarrier object at the location specified by the address operand addr. The invalidation is supported for all layouts described in Layouts of the mbarrier object. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

mbarrier.inval invalidates the mbarrier object at the location specified by the address operand addr. The invalidation is supported for all layouts described in Layouts of the mbarrier object. An mbarrier object must be invalidated before using its memory location for any other purpose. Performing any mbarrier operation except mbarrier.init on a memory location that does not contain a valid mbarrier object, results in undefined behaviour. If no state space is specified then Generic Addressing is used. (see the official PTX ISA docs for the full description)

Examples

.shared .b64 shmem;
.reg    .b64 addr;
.reg    .b32 %r1;
.reg    .pred t0;

// Example 1 :
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources