mbarrier.init GPU Virtual ISA NVIDIA

mbarrier.init Parallel Synchronization and Communication Instructions

mbarrier.init{.layout}{.shared{::cta}}.b64 [addr], count;

mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.0
Minimum Target sm_80

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
mbarrier.init{.layout}{.shared{::cta}}.b64 [addr], count; sm_80 mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count. The. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

mbarrier.init initializes the mbarrier object at the location specified by the address operand addr with the unsigned 32-bit integer count. The.layout qualifier specifies the layout that is used to initialize the mbarrier object. If not specified explicitly, a.layout::v0 mbarrier is initialized. Refer Layouts of the mbarrier object for more details. The valid range of values for the operand count varies depending upon.layout as specified below: [1, …, 2 20 - 1] for mbarrier with.layout::v0 [1, …, 2 9 - 1] for mbarrier with.layout::v1 The constituents of the mbarrier object are initialized as follows: The primary and conditional phases are initialized to zero. (see the official PTX ISA docs for the full description)

Examples

.shared .b64 shMem, shMem2, shMem3;
.reg    .b64 addr;
.reg    .b32 %r1;

cvta.shared.u64          addr, shMem2;
mbarrier.init.b64        [addr],   %r1;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources