barrier.cluster GPU Virtual ISA NVIDIA

barrier.cluster Parallel Synchronization and Communication Instructions

barrier.cluster.arrive{.sem}{.aligned};

Performs barrier synchronization and communication within a cluster.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 7.8
Minimum Target sm_90

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
barrier.cluster.arrive{.sem}{.aligned}; sm_90 Performs barrier synchronization and communication within a cluster. barrier.cluster instructions can be used by the threads within the cluster for synchronization and communication. barrier.cluster. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

Performs barrier synchronization and communication within a cluster. barrier.cluster instructions can be used by the threads within the cluster for synchronization and communication. barrier.cluster.arrive instruction marks warps’ arrival at barrier without causing executing thread to wait for threads of other participating warps. barrier.cluster.wait instruction causes the executing thread to wait for all non-exited threads of the cluster to perform barrier.cluster.arrive. In addition, barrier.cluster instructions cause the executing thread to wait for all non-exited threads from its warp. When all non-exited threads in the cluster have executed barrier.cluster. (see the official PTX ISA docs for the full description)

Examples

// use of arrive followed by wait
ld.shared::cluster.u32 r0, [addr];
barrier.cluster.arrive.aligned;
...
barrier.cluster.wait.aligned;
st.shared::cluster.u32 [addr], r1;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources