multimem.red.async GPU Virtual ISA NVIDIA

multimem.red.async Parallel Synchronization and Communication Instructions

multimem.red.async.sem.scope{.ss}.op.type [a], b;

multimem.red.async is a non-blocking instruction which initiates an asynchronous reduction operation specified by.op, with operand b and the value at memory locations residing on each GPU’s memory referred to by the destination multimem address operand a.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 9.3
Minimum Target sm_90

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
multimem.red.async.sem.scope{.ss}.op.type [a], b; sm_90 multimem.red.async is a non-blocking instruction which initiates an asynchronous reduction operation specified by. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

multimem.red.async is a non-blocking instruction which initiates an asynchronous reduction operation specified by.op, with operand b and the value at memory locations residing on each GPU’s memory referred to by the destination multimem address operand a. Address operand a must be a multimem address. Otherwise, the behavior is undefined.

Examples

// Asynchronous add reduction, GPU scope, explicit .global, 32-bit unsigned.
multimem.red.async.release.gpu.global.add.u32 [mm_addr], src_u32;

// System scope, generic addressing.
multimem.red.async.release.sys.add.s32 [mm_addr], src_s32;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources