fence GPU Virtual ISA NVIDIA

fence Parallel Synchronization and Communication Instructions

// Thread fence:
fence{.sem}.scope;

The fence instruction establishes an ordering between memory accesses requested by this thread, as described by the memory consistency model.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.4
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
// Thread fence: fence{.sem}.scope; sm_20 The fence instruction establishes an ordering between memory accesses requested by this thread, as described by the memory consistency model.

Operands

  • Thread fence:
    Operand

At a Glance

Data Types -

Related AMDGPU Concepts

Memory Fence ↗
equivalent sequence

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

The fence instruction establishes an ordering between memory accesses requested by this thread (ld, st, atom and red instructions), as described by the memory consistency model. fence.acq_rel is a light-weight fence sufficient for memory synchronization in most programs, while fence.sc is a slower fence that can restore sequential consistency when used in sufficient places, at the cost of performance. The legacy membar instruction covers the thread-scope membar.level forms.

Examples

membar.gl;
membar.cta;
membar.sys;
fence.sc.cta;
fence.sc.cluster;
fence.proxy.alias;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources