Memory Fence Synchronization
Order this thread's prior memory accesses relative to later ones, visible to a specified scope.
Vendor-Neutral Definition
All memory operations issued by the executing thread before the fence become visible, in program order, to other threads within the specified scope, before any memory operation issued after the fence.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent sequence
AMDGPU has no single fence opcode matching PTX membar; ordering is expressed through wait-count instructions instead.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | membar | no single matching opcode — see restrictions |
| ISA Layer | Virtual | Native |
| Data Types | — | — |
| Version / Target Introduced | PTX ISA 2.0 |
Important Differences
- AMDGPU expresses memory ordering via s_waitcnt on the vmcnt/lgkmcnt/expcnt counters, which track in-flight vector-memory, LDS/scalar-memory, and export operations respectively — a sequence, not a single fence instruction.
Source Evidence
- Parallel Thread Execution ISA ↗ — NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ — LLVM Project
Verification method: documentation