membar GPU Virtual ISA NVIDIA

Memory Barrier / Fence Synchronization

membar.level;

Order this thread's prior memory accesses relative to later ones, visible to a given scope.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 2.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
membar.level; cta, gl, sys sm_20 level selects the visibility scope: CTA, whole GPU, or system (including other GPUs/host).

Operands

At a Glance

Data Types —
Modifiers cta, gl, sys

Related AMDGPU Concepts

Memory Fence ↗
equivalent sequence

Reference

NVIDIA PTX ISA

Semantics

All memory operations issued by this thread before the fence become visible, in order, to other threads within the given scope before any operation issued after the fence.

Sources