bar.cta GPU Virtual ISA NVIDIA

bar.cta Parallel Synchronization and Communication Instructions

bar.cta.sync a{, b};

Performs barrier synchronization and communication within a CTA.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_20

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
bar.cta.sync a{, b}; sm_20 Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen barriers numbered 0..15. barrier{. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Workgroup Barrier ↗
equivalent with restrictions
s_barrier (AMDGPU)

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen barriers numbered 0..15. barrier{.cta} instructions can be used by the threads within the CTA for synchronization and communication. Operands a, b, and d have type.u32; operands p and c are predicates. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. If no thread count is specified, all threads in the CTA participate in the barrier. When specifying a thread count, the value must be a multiple of the warp size. (see the official PTX ISA docs for the full description)

Examples

// Use bar.sync to arrive at a pre-computed barrier number and
// wait for all threads in CTA to also arrive:
    st.shared [r0],r1;  // write my result to shared memory
    bar.cta.sync  1;    // arrive, wait for others to arrive
    ld.shared r2,[r3];  // use shared results from other threads
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources