s_barrier GPU Native ISA AMD Scalar

Barriers

s_barrier

Synchronize all waves of the executing workgroup at this point.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0001010
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 10 in OP rebuilds 0xBF8A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 61), AMD RDNA 3 (opcode 61). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 2, AMD RDNA 1.

Format SOPP
Width 32 bits
Opcode 10
Identifier 0xBF8A0000
Execution Unit Scalar ALU

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Workgroup Barrier ↗
equivalent with restrictions
barrier (PTX)
bar.cta (PTX)
barrier.cta (PTX)

Related

More in Barriers

Reference

AMDGPU / GFX ISA

Description

Synchronize waves within a threadgroup.

Semantics

Every wave belonging to the workgroup blocks until all waves of that workgroup have executed s_barrier.

Example

s_barrier   // block until every wave in the workgroup arrives here

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources