s_barrier GPU Native ISA AMD Scalar

S BARRIER Barriers

s_barrier

Synchronize all waves of the executing workgroup at this point.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOPP) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOPP
Width 32 bits
Execution Unit Scalar ALU

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Workgroup Barrier ↗
equivalent with restrictions
barrier (PTX)
bar.cta (PTX)
barrier.cta (PTX)

Related

More in Barriers

Reference

AMDGPU / GFX ISA

Description

Synchronize waves within a threadgroup.

Semantics

Every wave belonging to the workgroup blocks until all waves of that workgroup have executed s_barrier.

Example

s_barrier   // block until every wave in the workgroup arrives here

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources