vote GPU Virtual ISA NVIDIA

Vote Parallel Synchronization and Communication Instructions

vote.mode.pred d, {!}a;

Combine a per-lane predicate across the warp using any/all/ballot reduction.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.0
Minimum Target sm_12

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
vote.mode.pred d, {!}a; any, all, uni sm_12 Reduce predicate a across the warp: any true, all true, or all-lanes-agree.
vote.ballot.b32 d, {!}a; ballot sm_20 Collect per-lane predicate a into a 32-bit bitmask, one bit per lane.

Operands

  • d
    Destination register or predicate
  • a
    Per-lane predicate operand

At a Glance

Data Types -
Modifiers all, any, ballot, uni

Related AMDGPU Concepts

Ballot ↗
equivalent sequence
Warp Vote ↗
equivalent sequence
v_cmp_eq_u32 (AMDGPU)
s_cmp_eq_u32 (AMDGPU)

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

vote.sync will cause executing thread to wait until all non-exited threads corresponding to membermask have executed vote.sync with the same qualifiers and same membermask value before resuming execution. Operand membermask specifies a 32-bit integer which is a mask indicating threads participating in this instruction where the bit position corresponds to thread’s laneid. Operand a is a predicate register. In the mode form, vote.sync performs a reduction of the source predicate across all non-exited threads in membermask. (see the official PTX ISA docs for the full description)

Semantics

d = reduction of predicate a across the active lanes of the warp, per the selected mode.

Examples

vote.sync.all.pred    p,q,0xffffffff;
vote.sync.ballot.b32  r1,p,0xffffffff;  // get 'ballot' across warp

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources