vote GPU Virtual ISA NVIDIA

Vote Warp-Level

vote.mode.pred d, {!}a;

Combine a per-lane predicate across the warp using any/all/ballot reduction.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding — the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.2
Minimum Target sm_12

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations — each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
vote.mode.pred d, {!}a; any, all, uni sm_12 Reduce predicate a across the warp: any true, all true, or all-lanes-agree.
vote.ballot.b32 d, {!}a; ballot sm_20 Collect per-lane predicate a into a 32-bit bitmask, one bit per lane.

Operands

  • d
    Destination register or predicate
  • a
    Per-lane predicate operand

At a Glance

Data Types —
Modifiers all, any, ballot, uni

Related AMDGPU Concepts

Ballot ↗
equivalent sequence

Reference

NVIDIA PTX ISA

Semantics

d = reduction of predicate a across the active lanes of the warp, per the selected mode.

Sources