Ballot Warp/Wavefront-Level
Collect a 1-bit predicate from every lane of a warp/wavefront into a single bitmask.
Vendor-Neutral Definition
result = bitmask where bit i is the predicate value contributed by lane i (for active lanes); used to reason about which lanes agree on a condition.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent sequence
AMDGPU has no single ballot opcode; the equivalent bitmask is obtained from a per-lane compare's execution-mask-width destination.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | vote | no single matching opcode — see restrictions |
| ISA Layer | Virtual | Native |
| Data Types | — | — |
| Version / Target Introduced | PTX ISA 1.2 |
Important Differences
- The equivalent result comes from executing a per-lane compare (e.g. v_cmp_eq_u32) into the EXEC-mask-width destination (VCC or an SGPR pair), which the caller then reads as the ballot bitmask — this is a compiler-emitted sequence, not a single matching opcode.
Source Evidence
- Parallel Thread Execution ISA ↗ — NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ — LLVM Project
Verification method: documentation