activemask GPU Virtual ISA NVIDIA

Active Mask Parallel Synchronization and Communication Instructions

activemask.b32 d;

Query the bitmask of currently active (converged) lanes in the executing warp.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.2
Minimum Target sm_30

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
activemask.b32 d; sm_30 Reads the current active-lane mask with no side effects and no synchronization.

Operands

  • d
    Destination register receiving the active-lane bitmask

At a Glance

Data Types -

Related AMDGPU Concepts

Execution Mask Manipulation ↗
equivalent with restrictions
s_mov_b64 (AMDGPU)
s_wqm_b64 (AMDGPU)

Related

More in Parallel Synchronization and Communication Instructions

Reference

NVIDIA PTX ISA

Description

activemask queries predicated-on active threads from the executing warp and sets the destination d with 32-bit integer mask where bit position in the mask corresponds to the thread’s laneid. Destination d is a 32-bit destination register. An active thread will contribute 1 for its entry in the result and exited or inactive or predicated-off thread will contribute 0 for its entry in the result.

Semantics

d = bitmask of lanes currently active/converged at this point in the warp.

Examples

activemask.b32  %r1;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources