Execution Mask Manipulation Warp/Wavefront-Level

Read or modify the mask that decides which lanes of a warp or wavefront are active.

Vendor-Neutral Definition

Divergent control flow is implemented by disabling lanes rather than by branching each one separately. The question is whether that mask is an architectural register the program may write, or hidden state the hardware manages.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler translations.
equivalent with restrictions AMDGPU exposes EXEC as a writable architectural register and implements divergence with explicit instructions. PTX hides the mask and lets a program observe it but not set it.
Property NVIDIA PTX AMDGPU
Instruction activemask s_and_saveexec_b64, s_mov_b64, s_wqm_b64
ISA Layer Virtual Native
Data Types - b64
Version / Target Introduced PTX ISA 6.2 gfx1100, gfx1100, gfx1100

Important Differences

  • This is the deepest difference between the two models. On AMDGPU, an if statement compiles to s_and_saveexec_b64: compute a lane mask, AND it into EXEC, keep the old value to restore afterwards. The mask is ordinary data in an SGPR pair.
  • PTX has no writable equivalent. activemask reads which lanes are currently converged, and since Volta the hardware schedules lanes independently, so even the reconvergence point is not something the program controls directly.
  • s_wqm_b64 has no PTX counterpart at all: whole quad mode activates lanes that are inactive, so that a helper lane can supply values for derivative and texture-gradient calculations.

Source Evidence

Verification method: documentation