s_mov_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_mov_b64

Move scalar input into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00000001
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 1 in OP rebuilds 0xBE800100, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 4), AMD RDNA 1 (opcode 4). The same in AMD CDNA 4, AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOP1
Width 32 bits
Opcode 1
Identifier 0xBE800100

Operands

  • SDST
    Written. All scalar destination operands. Data format: 64 bits of arbitrary data. (OPR_SDST, FMT_NUM_B64)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 64 bits of arbitrary data. (OPR_SSRC, FMT_NUM_B64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Execution Mask Manipulation ↗
equivalent with restrictions
activemask (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.b64 = S0.b64

Example

s_mov_b64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources