s_lshl1_add_u32 GPU Native ISA AMD Scalar
S LSHL1 ADD U32 Scalar Arithmetic
s_lshl1_add_u32
Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.
Semantics
tmp = (64'U(S0.u32) << 1U) + 64'U(S1.u32);
SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U;
// unsigned overflow.
D0.u32 = tmp.u32
Example
s_lshl1_add_u32 s0, 0, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 107. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project