s_getreg_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_getreg_b32

Read some or all of a hardware register into the LSBs of destination.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
10001
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 17 in OP rebuilds 0xB8800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 18), AMD RDNA 1 (opcode 18). The same in AMD CDNA 4, AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPK
Width 32 bits
Opcode 17
Identifier 0xB8800000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 32 bits of arbitrary data. (OPR_SDST, FMT_NUM_B32)
  • SIMM16
    Read. Reference to a hardware register that is manipulated by getreg or setreg. This operand encodes the ID of the register to access and allows access to a subset of the full register by specifying an offset and size in bits. Data format: 16 bits of arbitrary data. (OPR_HWREG, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_getreg_b32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopk.s). Not from an AMD document, and not authored here.

Sources