s_cvt_pk_rtz_f16_f32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cvt_pk_rtz_f16_f32

Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding…

Encoding

Binary Layout (AMD CDNA 5)
10
31:30
1001000
29:23
SDST
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 72 in OP rebuilds 0xA4000000, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format SOP2
Width 32 bits
Opcode 72
Identifier 0xA4000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SDST, FMT_NUM_PK2_F16)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP2 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding mode), and store the result into a scalar register.

Example

s_cvt_pk_rtz_f16_f32 s5, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1150_asm_salu_float.s). Not from an AMD document, and not authored here.

Sources