s_cvt_pk_rtz_f16_f32 GPU Native ISA AMD Scalar
S CVT PK RTZ F16 F32 Scalar Arithmetic
s_cvt_pk_rtz_f16_f32
Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding mode), and store the result into a scalar register.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.