s_cvt_u32_f32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cvt_u32_f32

Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
01100111
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 103 in OP rebuilds 0xBE806700, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format SOP1
Width 32 bits
Opcode 103
Identifier 0xBE806700

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 32-bit integral data. (OPR_SDST, FMT_NUM_U32)
  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 32-bit single-precision floating point value. (OPR_SSRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_cvt_u32_f32 s5, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1150_asm_salu_float.s). Not from an AMD document, and not authored here.

Sources