s_ff1_i32_b32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_ff1_i32_b32

Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits in the input.

Also written as s_ctz_i32_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00010000
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 16 in OP rebuilds 0xBE801000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 19), AMD RDNA 1 (opcode 19). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 16
Identifier 0xBE801000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = -1; // Set if no ones are found for i in 0 : 31 do // Search from LSB if S0.u32[i] == 1'1U then tmp = i; break endif endfor; D0.i32 = tmp

Example

S_FF1_I32_B32(0xaaaaaaaa) => 1
S_FF1_I32_B32(0x55555555) => 0
S_FF1_I32_B32(0x00000000) => 0xffffffff
S_FF1_I32_B32(0xffffffff) => 0

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources