s_ff0_i32_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_ff0_i32_b64

Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00001111
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 15 in OP rebuilds 0xBE800F00, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 18), AMD RDNA 1 (opcode 18). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 15
Identifier 0xBE800F00

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_I32)
  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. Store -1 if there are no "0" bits in the input.

Semantics

tmp = -1; // Set if no zeros are found for i in 0 : 63 do // Search from LSB if S0.u64[i] == 1'0U then tmp = i; break endif endfor; D0.i32 = tmp

Example

s_ff0_i32_b64 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_sop.s). Not from an AMD document, and not authored here.

Sources