s_get_shader_cycles_u64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_get_shader_cycles_u64

AMDGPU SOP1 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
101111101
31:23
SDST
22:16
00000110
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 6 in OP rebuilds 0xBE800600, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOP1
Width 32 bits
Opcode 6
Identifier 0xBE800600

Operands

  • SDST
    Written. All scalar destination operands. Data format: Unsigned 64-bit integral data. (OPR_SDST, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_get_shader_cycles_u64 vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop1.s). Not from an AMD document, and not authored here.

Sources