s_getpc_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_getpc_b64

Store the address of the next instruction to a scalar register.

Also written as s_get_pc_i64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111101
31:23
SDST
22:16
00011100
15:8
SSRC0
7:0
 

The ENC_SOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 28 in OP rebuilds 0xBE801C00, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 4 (opcode 71), AMD RDNA 3.5 (opcode 71), AMD RDNA 3 (opcode 71), AMD RDNA 2 (opcode 31), AMD RDNA 1 (opcode 31). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOP1
Width 32 bits
Opcode 28
Identifier 0xBE801C00

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_B64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOP1 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This instruction must be 4 bytes.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Store the address of the next instruction to a scalar register. The byte address of the instruction immediately following this instruction is saved to the destination.

Semantics

D0.i64 = PC + 4LL

Example

s_getpc_b64 vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources