s_getpc_b64 GPU Native ISA AMD Scalar
S GETPC B64 Scalar Arithmetic
s_getpc_b64
Store the address of the next instruction to a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
This instruction must be 4 bytes.
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Store the address of the next instruction to a scalar register. The byte address of the instruction immediately following this instruction is saved to the destination.
Semantics
D0.i64 = PC + 4LL
Example
s_getpc_b64 vccA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 123. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project