s_ff0_i32_b32 GPU Native ISA AMD Scalar

S FF0 I32 B32 Scalar Arithmetic

s_ff0_i32_b32

Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. Store -1 if there are no "0" bits in the input.

Semantics

tmp = -1; // Set if no zeros are found for i in 0 : 31 do // Search from LSB if S0.u32[i] == 1'0U then tmp = i; break endif endfor; D0.i32 = tmp

Example

S_FF0_I32_B32(0xaaaaaaaa) => 0
S_FF0_I32_B32(0x55555555) => 1
S_FF0_I32_B32(0x00000000) => 0
S_FF0_I32_B32(0xffffffff) => 0xffffffff

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources