s_cmpk_eq_u32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_cmpk_eq_u32

Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant.

Encoding

Binary Layout (AMD CDNA 4)
1011
31:28
01000
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 8 in OP rebuilds 0xB4000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 9), AMD RDNA 3 (opcode 9), AMD RDNA 2 (opcode 9), AMD RDNA 1 (opcode 9). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOPK
Width 32 bits
Opcode 8
Identifier 0xB4000000

Operands

  • SDST
    Read. N/A Data format: N/A (OPR_SDST, FMT_NUM_U32)
  • SIMM16
    Read. 16-bit integer constant. Data format: N/A (OPR_SIMM16, FMT_NUM_U16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

SCC = S0.u32 == 32'U(S1.u16)

Example

s_cmpk_eq_u32 s0, 0x1234

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources