s_call_b64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_call_b64

Store the address of the next instruction to a scalar register and then jump to a constant offset relative to the current PC.

Also written as s_call_i64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
1011
31:28
10101
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 21 in OP rebuilds 0xBA800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 4 (opcode 20), AMD RDNA 3.5 (opcode 20), AMD RDNA 3 (opcode 20), AMD RDNA 2 (opcode 22), AMD RDNA 1 (opcode 22). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SOPK
Width 32 bits
Opcode 21
Identifier 0xBA800000

Operands

  • SDST
    Written. N/A Data format: N/A (OPR_SDST, FMT_NUM_B64)
  • SIMM16
    Read. A relative jump offset. Data format: N/A (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_call_b64 vcc, 12609

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_sopk.s). Not from an AMD document, and not authored here.

Sources